1. Field of the Invention
This invention relates to a semiconductor memory device and to a method of fabricating the same. More particularly, it relates to a DRAM having memory cells, each including a capacitor and to a transistor and a method of fabricating the same.
2. Description of the Related Art
In a conventional method of fabricating a semiconductor memory device having memory cells, an element isolation insulating film is formed on the surface of a semiconductor substrate by LOCOS process and then the memory cells are formed. However, since bird's beaks develop during the formation of this element isolation insulating film, the prior art method involves a problem that a semiconductor memory device having memory cells integrated at a high density cannot be fabricated so easily.
To solve this problem, as disclosed, for example, in "Isolation Process Using Polysilicon Buffer Layer for Scaled MOS/VSLI", Yu-Pin Han and Ring Ma, The Electrochemical Society Extended Abstract, 1984 and JP-A-63-302536, an improved LOCOS process using a polysilicon buffer layer for the formation of the element isolation insulating film has been proposed to reduce the bird's beaks.
A method of fabricating a semiconductor memory device using a polysilicon buffer layer will be explained with reference to FIGS. 3A and 3B. First of all, an element isolation insulating film 102 is formed on the surface of a silicon substrate 101 by an improved LOCOS process using a polysilicon buffer layer as shown in FIG. 3A, and capacitor trenches 103 are then formed by a reactive ion etching (RIE) process. Next, a first capacitor electrode film 104, a capacitor insulating film 105, a second capacitor electrode film 106, a gate insulating film 107, a gate electrode 108 and diffusion layers 109 to serve as drain and source regions of a transistor are successively formed.
According to this method using the polysilicon buffer layer, however, the step of forming the polysilicon layer is necessary. Therefore, the steps become more complicated, and a design margin is necessary in consideration of an alignment error of a mask at the exposure step of forming the element isolation insulating film and deviation in the process. For these reasons, there is a limit in reducing the width of the element isolation insulating film, and it is indeed difficult to satisfactorily integrate the memory cells at a high density.